Semiconductor devices are typically interconnected by patterned electrically conductive layers of high conductivity metal or metal alloy, commonly referred to as interconnects or interconnect wires. Complex circuits require very close spacing of interconnect wires and multiple levels of metalization to interconnect the semiconductor devices. Interconnects are made by depositing and patterning alternating layers of a conductive material and layers of an insulating dielectric material. In multilevel interconnects, small holes or contact vias are formed through the dielectric layers and filled with conductive material to interconnect the conductive layers.
The interlevel dielectric material is typically SiO2, which has a dielectric constant, k, of about 4.0. Efforts have been made to replace the SiO2 dielectric with materials having lower dielectric constants. As used herein, a low dielectric material or low-k material means a material having a dielectric constant, k, of lower than about 3.5 and preferably lower than about 3. As used herein, a high dielectric material or high-k material means a material having a dielectric constant, k, of higher than about 3.5 and preferably about 4.0.
With today's more demanding circuit density, wirability, array-I/O architecture and receiver performance requirements, semiconductor chip performance is requiring the transition from Al to Cu interconnects because of the impact of interconnect RC delay on MOSFET gate delay analysis. The interconnect delay components become a larger percentage of the total CMOS gate delay as the intrinsic delay decreases and must be reduced either through interconnect resistance or capacitance reduction. Interconnect RC delay can be reduced by migrating from Al- to Cu-based interconnects, which improves electrical conductivity.
The transition from Al to Cu interconnects is not only important for semiconductor chip performance objectives, it is also important for ESD robustness in high-performance chips. Aluminum interconnects are a significant ESD failure mechanism in high-pin-count microprocessor chips. The migration from Al- to Cu-based interconnects achieved a two-fold improvement in critical current density-to-failure, Jcrit, in a SiO2 ILD. The Al-to-Cu technology migration path led to continuous ESD improvement, allowing for metal film thickness and line width scaling.
The interconnect component of gate RC delay can be further reduced (i.e. line to line capacitance) by using low-k materials instead of SiO2 ILD. Cu interconnects and low-k materials enable the semiconductor industry to meet signal-delay requirements down to at least 100 nm technology.
Low-k materials must also have low leakage, a low thermal coefficient of expansion, high breakdown voltage, low film stress, high cracking resistance and compatibility and integrability with Cu interconnects. Low-k materials include, for example, silicon oxyfluoride (FxSiOy), hydrogen silsequioxane (HSQ), organic polymers such as poly(arelene) ethers, benzoncyclobutene (BCB), nanoporous silica and porous polymers. Other low-k materials such as, for example, Silicon Low-k (SiLK) from Dow Chemical Corp., Midland, Mich., having suitable material properties, compatibility with Cu interconnects, and the desired electrical permittivity will be known to those skilled in the art.
From an ESD perspective, the thermal properties of low-k materials are key to understanding the ESD robustness of Cu interconnect systems and the scaling implications on ESD robustness. Low-k materials have different thermal and mechanical properties which are a significant deviation from SiO2 dielectrics. The mass density, thermal conductivity, and the specific heat all influence the thermal characteristics of the ILD through the thermal resistance and thermal capacity. Models have been developed for determining the power-to-failure and critical-current-density-to-failure in the thermal diffusion time scale for various interconnect structures, as described in S. Voldman et al., “High-Current Characterization of Dual-Damascene Copper Interconnects in SiO2 and Low-k Interlevel Dielectrics for Advanced CMOS Semiconductor Technologies,” International Reliability Physics Symposium, Mar. 22, 1999.
The trend in the industry, especially with integrated circuits, has been to use low-k materials near the interconnect wires to improve the performance of the circuit. For example, U.S. Pat. Nos. 5,744,865 and 5,821,621 disclose interconnect structures having a low-k material placed between the multiple wires of the interconnect. The low-k material reduces the capacitance of the interconnect and helps reduce crosstalk noise between adjacent wires carrying different signals from different pads. However, the interconnects surrounded by low-k materials are not well suited for applications where ESD robustness is more important than performance, such as interconnects between pads and ESD devices or other devices for discharging or sinking a current. Such applications are the focus of the present invention.